1. Field of the Invention
The present invention relates to semiconductor integrated circuit devices, and particularly to a semiconductor integrated circuit device that operates in synchronization with an external clock signal. More particularly, the present invention relates to, for example, a synchronous semiconductor memory device that operates in synchronization with an external clock signal.
2. Description of the Background Art
In accordance with increase in the operating speed of recent microprocessors (referred to as MPU hereinafter), a synchronous DRAM that operates in synchronization with a clock signal and the like (synchronous DRAM: referred to as SDRAM hereinafter) are used to realize high speed access of dynamic random access memories (referred to as DRAM hereinafter) employed as the main storage device.
The internal operation of such SDRAMs is divided into the row related operation and column related operation for control.
To allow further increase in the operation speed in a SDRAM, a bank structure is employed where memory cell arrays are divided into a plurality of banks that are operable independently. In other words, the operation of each bank is under independent control for a row related operation and a column related operation.
However, further increase in the high speed operation is required for a semiconductor memory device depending upon the applied system.
In contrast, some systems do not require such a high speed operation. When a SDRAM designed to correspond to a system that requires maximum speed is used in a system that allows a lower operating frequency, it is not desirable from the standpoint of power consumption to operate the SDRAM according to the specification of the highest speed.
Also, the manner of synchronous operation for the entire system differs. There are systems having a reference clock signal for synchronous operation output from only the controller end, and systems in which a synchronizing clock signal is output equally to each control device and semiconductor memory device forming the system.
It may be necessary to modify the operation mode of the SDRAM itself in the above two cases to operate faster taking account of the effect of skew of a clock signal.
If a different design is to be provided according to each particular application, the cost required for designing and fabrication will increase.
In accordance with increase in the speed of the throughput of the DRAM becoming a critical issue in the system performance, a SDRAM that inputs/outputs data in synchronization with an externally applied clock is now popular instead of the DRAM of the EDO method.
The SDRAM method has the data, address, and various commands input into the chip in synchronization with the rising edge of an externally applied clock with the internal process of the memory chip partially carried out in synchronization with the clock, and has the output also provided in synchronization with the edge of the external clock.
In system applications where a great amount of data is to be processed at high speed such as image data, a further higher throughput is required.
To this end, a double data rate synchronous DRAM (referred to as DDR-SDRAM hereinafter) has been proposed as a new input/output method of a DRAM. An external strobe clock for data is applied, and data is input in synchronization with both the rising and falling edges. An internal strobe clock in synchronization with the data output is provided.
FIG. 77 shows a block diagram of an example of this DDR-SDRAM. Only the data input/output through one data input/output terminal is depicted in the drawing.
In a data writing operation, the data input in synchronization with a strobe clock from a pad 9000 passes through the input buffer to be held in an input register. Here, the data input at the rise of a clock and the data input at the fall of the clock are held in separate input registers 9002 and 9003.
The input control circuit switches a connection switch 9004 for the data bus and the register according to whether the address is even or odd.
Following the latency of the data strobe clock, the data is provided to the internal data bus in synchronization with the clock. In general, two clocks are set as the latency of the data strobe. The memory array is divided depending whether the address is even or odd. Data is received from respective corresponding data buses to be stored into a corresponding memory cell. When data is written continuously, address counters 9006 and 9007 generate the required addresses, which are sent to the memory array.
Here, address counters 9006 and 9007 generate different patterns depending upon whether the corresponding memory array is at an even address or an odd address.
In a data reading operation, data is read out from a corresponding memory cell according to the address sent to the memory array from address counters 9006 and 9007 to be output to the data bus.
Output control circuit 9008 alters the connection between the data bus and the output register depending upon whether the address is an uneven number or an odd number. The data is temporarily stored in the register. Output control circuit 9008 switches switch 1012 in accordance with the set latency to output data alternately that are latched in output registers 9009 and 9010 in synchronization with the rising and falling edges of the clock.
In the above-described system, it was necessary to produce different chips depending upon whether the SDRAM takes the single data rate system (referred to as SDR-DRAM hereinafter) or the double data rate system despite similarity in the chip internal operation.
In view of the foregoing, an object of the present invention is to provide a synchronous semiconductor memory device that can adjust the margin of chip operation flexibly with respect to an external clock signal according to the system requirement.
Another object of the present invention is to provide a synchronous semiconductor memory device that allows implementation of a single data rate SDRAM and a double data SDRAM with the same chip.
A further object of the present invention is to provide a synchronous semiconductor memory device that can ensure an operation margin sufficient for an external clock signal according to the system.
According to an aspect of the present invention, a synchronous semiconductor memory device receiving an address signal and a control signal in synchronization with an external clock signal includes a memory cell array, a control circuit, a first internal synchronizing signal generation circuit, a second internal synchronizing signal generation circuit, an address signal input circuit, a control signal input circuit, a memory cell select circuit, a plurality of data input/output nodes, and an interface circuit.
The memory cell array includes a plurality of memory cells arranged in a matrix. The control circuit controls the operation of the synchronous semiconductor memory device. The first internal synchronizing signal generation circuit outputs a first internal clock signal synchronized with the external clock signal and having a frequency higher than that of the external clock signal. The second internal synchronizing signal generation circuit outputs a second internal clock signal synchronized with the external clock signal.
The address signal input circuit inputs an address signal in synchronization with the second internal clock signal. The control signal input circuit inputs a control signal in synchronization with the second internal clock signal. The memory cell select circuit selects a memory cell according to the address signal.
The plurality of data input/output nodes receive write data to a memory cell or read out data from a memory cell. The interface circuit is provided between a memory cell selected by the select circuit and a data input/output node to transfer write data.
The interface circuit effects input of write data from each of a plurality of data input/output nodes in synchronization with the second internal clock signal in a first operation mode, and effects input of write data from each of the plurality of data input/output nodes in synchronization with the first internal clock signal in a second operation mode.
Preferably, the memory cell array is a bank divided into a plurality of memory cell blocks, allowing a read operation and a write operation independently. The synchronous semiconductor memory device further includes an address bus, a command data bus, a first variable vernier circuit, and a second variable vernier circuit.
The address bus is provided in common to the plurality of memory cell blocks to transmit an address signal from the address signal input circuit. The command data bus is provided in common to the plurality of memory cell blocks to transmit the internal control signal output from the control circuit. The first variable vernier circuit adjusts the delay amount of the signal transmitted through the address bus under control of the control circuit. The second variable vernier circuit adjusts the delay amount of the signal transmitted through the command data bus under control of the control circuit.
The memory cell select circuit includes a plurality of local select circuits provided corresponding to the memory cell blocks to select a memory cell according to the address signal from the address bus. Each local select circuit is rendered active in response to selection of a corresponding memory cell block according to an internal control signal and an address signal.
According to still another aspect of the present invention, a synchronous semiconductor memory device that inputs a row address signal and a column address signal in synchronization with an external clock signal includes a memory cell array, an internal synchronizing signal generation circuit, an address signal input circuit, a row select circuit, and a column select circuit.
The memory cell array includes a plurality of memory cells arranged in a matrix. The memory cell array includes a plurality of memory cell blocks.
The internal synchronizing signal generation circuit provides an internal clock signal in synchronization with the external clock signal. The address signal input circuit inputs row and column address signals in synchronization with the internal clock signal.
The row select circuit is provided corresponding to a memory cell block to select a memory cell row according to a row address signal. The row select circuit includes a first retain circuit for retaining a row address signal from the address signal input circuit.
The column select circuit is provided corresponding to a memory cell block to select a memory cell column according to a column address signal. The column select circuit includes a second retain circuit for retaining a column address signal that is supplied in a time-divisional manner with respect to the row address signal, and a path select circuit for initiating a select operation of a memory cell column for data output prior to the end of a row select operation of the row select circuit according to the column address signal in the second retain circuit.
The main advantage of the present invention is that the margin of the chip operation can be adjusted flexibly with respect to an external clock signal according to the system requirement since the distribution of an internal clock signal can be modified according to external designing.
Another advantage of the present invention is that the operating margin can be improved allowing each bank to be operated with difference in phase. Therefore, an array structure optimum with respect to system change that improves the freedom of degree in array division in a multidivided array in addition to a high speed read out operation can be implemented.
Still another advantage of the present invention is that the read out operation can be carried out at high speed since the select operation of a memory cell column for data output is initiated prior to the end of a row select operation.